Hierarchical Constrained Coding for Floating-Gate to Floating-Gate Coupling Mitigation in Flash Memory

Flash memory comprises of grid of cells arranged in a rectangular lattice. A cell is a floating gate and the information is stored as charge in these floating gates. A multi-level-cell (MLC) can store more than one bit per cell. An ideal programming of a cell consists of injecting just the correct amount of charge in the cell by hot-electron injection. However, due to programming time constraints, some tolerance is accepted and the actual programming voltage is allowed to be within some range of the ideal. While programming a cell, due to the capacitive coupling between neighboring cells, the neighboring cells also get some charge. This phenomenon called as inter-cell-interference (ICI) can be from mild to extreme. Particularly, a cell at the lowest voltage level will pick up a lot of charge if its neighbors are then programmed to the highest level. In order to combat the noise due to ICI, constrained coding is a possible solution. Constrained coding consists of not allowing certain level patterns so that effects of ICI are contained. Constrained coding for solutions which have level information available while decoding all pages has been implemented for flash memory [1]. However, due to read latency requirements, level information may not be available while reading all pages and hence these codes cannot be used. We propose constrained codes which do not need level information while decoding all pages and hence average read latency requirements are met. Error propagation is a crucial degrading factor for constrained decoding and the codes we design are robust to channel noise. A new decoding algorithm which keeps synchronization which is crucial to contain error propagation is also proposed.