FPGA power consumption measurements and estimations under different implementation parameters

This paper investigates the effects of different design tool (Xilinx ISE) optimisation schemes on FPGA power consumption. Specifically, on-the-bench measurements are presented for eight highly popular security algorithms, which have been tested under a number of different synthesis and implementation optimisation scenarios. The algorithms under investigation are the BasicRSA, BasicDES, Camellia (with two distinct variations), TripleDES, AES, DES, and MD5. Finally, the efficiency of the design tool in generating accurate predictions on the power consumption of a specific design is also addressed. Results show that power consumption figures may vary from a 306mW reduction (compared to nominal design effort) to a 33mW increase and average improvement on the power consumption measured values ranges between 9.21% and −0.94% when different optimisation schemes are utilised. The Xilinx XPower Analyzer is also scrutinised; It provides estimates that are well above what is actually measured and the estimation error ranges between 17.5% to more than 200%. In the worst case, the XPower estimate is 307mW greater than the least power consumption value measured on-the-bench whereas it remains 258mW higher than the average value measured for the same algorithm and under all different optimisation scenarios. The least deviation in results is measured between 23mW and 31mW, however, the XPower estimate remains greater than that measured on-the-bench.