Versatile ultra low noise low power analog signal conditioning chip with integrated drivers

An ultra low-noise, low-power and miniature area analog signal conditioning chip in 180nm UMC Mixed-Mode CMOS process with 1.8V supply is presented. The design targets applications like sensors, biomedical and energy-efficient handheld devices. The test chip features Instrumentation Amplifier (INA) with chopper modulation at the first stage. The 2nd stage is a novel area efficient Spike Removal Filter (SRF). On-chip clock generators with frequency of 4kHz (non-overlapping) and 8kHz for SRF stage is implemented. The last stage is a differential active RC filter to adjust gain and bandwidth of the forward channel. The chip features a reconfigurable Driven-Right-Leg Circuit (DRLC) and Shield Drive Amplifier (SDA) in the feedback path specifically for Bio-medical applications. The DRLC is re-configurable with Operational amplifier (Op-Amp) and Operational Transconductance Amplifier (OTA). The measurement results show that INA achieves input-referred noise density of 28nV/√(Hz) and DC current of 5.9μA maintaining minimum CMRR of 109dB at 1.91kHz. Moreover, 34dB of 50Hz interference reduction is achieved with DRLC. Wide range of specifications along with reconfigurable modules and interconnections enables the chip for broad range of signal conditioning applications.