Hardening techniques for MRAM-based non-volatile storage cells and logic

Magnetic RAM (MRAM) is considered as a promising non-volatile memory technology for aerospace and avionic electronics thanks to its intrinsic hardness to radiation. Data is stored on the spin direction “up” and “down” of electrons instead of positive and negative charge. However, MRAM-based non-volatile storage cells and logic circuits are vulnerable to Single Event Effects (SEE) due to their CMOS peripheral circuits. Hardening techniques to mitigate SEE are presented in this paper. A new design of Radhard MRAM latch is firstly presented. TMR technique is then implemented on Configurable Logic Block to mitigate SET on data paths. By using 65 nm design kit and an MRAM compact model, hybrid simulations have been done to demonstrate the radiation hardness.