An improved fault tolerant architecture at CMOS level

A previous realization of a fault tolerant architecture at CMOS level, while guaranteeing the correct behavior of the circuit both in the fault-free situation and in the presence of stuck-on faults, was characterized by a neither null nor +V/sub dd/ output voltage when faults occurred. An improved architecture is here presented, which by adding additional transistors, achieves the fault tolerance property without degrading the performance of the circuit in terms of output voltage and short circuit current.