FPGA implementation of high performance FIR filters

This paper presents the design and implementation of high performance, high speed linear phase FIR filters using FPGA technology. Various well known multiplier architectures are compared and an appropriate structure for FPGA implementation is identified. The high data throughput required to accommodate the input sample values is achieved using an interleaved memory structure. To provide flexibility, a generic VHDL filter model has been developed which allows the automatic synthesis from specification down to FPGA realisation. The model operates on 2's complement numbers and is characterised by three user defined parameters: number of filter taps, signal and coefficient wordlengths. To demonstrate the design process, the implementation of a 64 tap linear phase filter with 60 dB attenuation at 0.28 fs, 12 dB attenuation at 0.25 fs and a passband ripple of /spl plusmn/0.01 dB up to 0.22 fs is included. The filter with 10 bit signal and 8 bit coefficient wordlength has been realised on a Xilinx XC4006E device and operates at a sampling frequency of 1.4 MHz.