New Reverse Converter Design of Moduli Set {2n, 2n+1-1, 2n-1}

An efficient design of the reverse converter for the three-moduli set {2ⁿ, 2ⁿ⁺¹-1, 2ⁿ-1} is presented in this paper. The reverse converter is structured by an adder based on New Chinese Remainder Theorem II (New CRT-II) conversion such that it can improve the hardware cost. The proposed conversion design is compared with the existing works based on the standard Cell TSMC 0.18μm CMOS technology. Under the same dynamic range(DR), the experimental results indicate that our design has better performance in terms of the area× delay × power. The proposed converter can achieve about average 46.596 % and 61.890 % reduction for those design with 4n-bit and 5n-bit dynamic range, respectively.