Analysis and architecture design of block matching in BM3D image denoising

In this paper, a low-cost VLSI implementation for Block Matching (BM) in BM3D image denoising with novel architectures of the slip window and SSD tree are presented. The experimental results show that the proposed technique preserves the BM3D denoising performance and obtains excellent performances in terms of less logic gate count and better visual quality. The design requires only low computational complexity and less SRAM for slip window. Its hardware cost is quite low, about 350k gates. Synthesis results show that the proposed design at a throughput about 177MB/s by using UMC 0.18um technology.