FPGA Implementation of Secure Time Shared Hash Stream Cipher

Hash functions are widely used in secure communication systems for message authentication and data integrity verification. For encryption of data, stream ciphers are preferred to block ciphers because it consumes less power and hardware. In this paper we propose implementation and analysis of a circuit for both Hash generation and Encryption of data, based on a single hardware block in the time shared manner. The design of stream cipher based on hardware efficient hash function was reported earlier but in a paper which appeared later, the security of this stream cipher was proved to be very low. In this paper, we investigate how to overcome this weakness and make the design more secure, without much increase in hardware complexity. Here, we implement a 128 bit message encryption circuit which facilitates data integrity check using hash function in FPGA.