Finding the worst case supply noise excitation methodology for high speed I/O interfaces

Most simultaneous switching output noise (SSO) validation of high speed interfaces such as PCIe, SATA, USB, Core logic etc is approached on a case to case basis. It's not always clear when these interfaces are put in a common validation eco-system and stressed concurrently, what will be the functionality and performance limiter. This paper describes a new methodology that maximizes the power supply noise droop of each High Speed I/O interfaces; by implementing a concurrent test in exercising PCIe, SATA and USB to actively transmit data on all the lanes on the electrical board; and at the same time; exerting power gate/ungate noise onto the chip to serve as a natural aggressor from the core logic into the I/O interfaces. To make matter worst, a test package is designed to merge all of these high speed interfaces and core logic power rail as one common power rail on the package so that the injected and coupling noise were maximized. The on-die noise measurements were measured and results were compiled and conclude the findings of this new methodology.