CMOS impedance spectrum analyzer with dual-slope multiplying ADC

We present a multi-channel, mixed-signal VLSI architecture that utilizes frequency response analysis (FRA) to extract the real and imaginary components of a biosensor impedance. Two computationally intensive operations, the multiplication and integration required by the FRA algorithm, are efficiently performed by an in-channel dual-slope multiplying ADC with minimal resources overhead. Multiplication of the input current by a digital coefficient is implemented by modulating the counter-controlled duration of the charging phase of the ADC. Integration is implemented by accumulating output digital bits in the ADC counter over multiple input samples. The 1.2mm×1.6mm prototype fabricated in a 0.13μm standard CMOS technology has been validated in DNA catalytic reporter detection. Each channel occupies an area of only 0.06mm² and consumes 42μW of power from a 1.2V supply.