A VLSI implementation of PDF computations in HMM based speech recognition

We present an architecture and VLSI implementation of the computations of Gaussian observation probabilities in HMM based speech recognition. As opposed to the previous work of Sagayama and Takahashi (see IEEE International Conf. on Acoustics, Speech and Signal Proc., vol.1, p.213-16, 1995), reducing the number of arithmetic operations is not the major concern when these computations are implemented in a standard CMOS process. Instead, the memory bandwidth is the limiting factor. We introduce a variant of the fix-point representation, called the dynamical circular fix-point format, which reduces the memory bandwidth requirements to one half of a traditional implementation and to the same as that of Sagayama et al. The memory requirements are reduced by a factor of 16 compared to Sagayama's method. The proposed solution has a simple hardware implementation and the speech recognizer performance degradation is insignificant.