A 40 MHz IF fourth-order double-sampled SC bandpass /spl Sigma//spl Delta/ modulator

A fully differential double-sampled SC architecture for a fourth-order bandpass /spl Sigma//spl Delta/ modulator is presented. This architecture is based on a double-sampled SC delay circuit. The effect of opamp DC gain on the notch frequency of this modulator is analyzed. The modulator is implemented in a 0.5 /spl mu/m CMOS technology and operates at a clock frequency of 80 MHz. Thus, the effective sampling rate is 160 MHz. The image signal is about 40 dB below the fundamental signal. Over a 2 MHz bandwidth centered at 40 MHz, the measured SNDR is 45 dB (not including the image). The circuit operates at 3.3 V and consumes 65 mW.