Comprehensive analysis of delay in UDSM CMOS circuits

In this paper, we have developed a simple and accurate delay model for any Ultra Deep Sub-micron (UDSM) CMOS inverter, NAND2 & NOR2 based on n
^th
power law of MOSFET model when the channel length is of the order of less than or equal to 90nm. We have taken all the parameters from BSIM.4.6.1 manual. This work derives analytical expression for the delay model of a CMOS inverter including all sorts of secondary effects such as Body Bias effect, Channel Length Modulation Effect (CLM), Velocity Saturation effect, Drain Induced Barrier Lowering (DIBL), etc which may occur in the Ultra Deep Submicron MOS devices. We also extend our delay model for 2 input CMOS NAND and NOR gate. Our result is better than nth power law and Cadence (UMC90nm) simulation result with respect to both quality and estimation time. Our proposed model gives an average error of only 3.63% with compare to Cadence Simulation result.