Optimization design of FPGA-based look-up-tables for linearizing RF power amplifiers

In this paper, a low-cost hardware implementation of a Look-up-Table(LUT) based digital predistorter (DPD) using Field Programmable Gate Array(FPGA) for power amplifier linearization is proposed. The LUT predistoter is implemented in Altera Stratix II DSP Development Board to simulate the inverse model for memoryless wide-band RF power amplifiers. The parameters of the LUT predistoter are identified using a dynamic exponential weighted moving average algorithm. This paper chooses the suitable table which is occupying less hardware resources from different tables by changing address width and word length for optimizing the design of LUT. Linearization performance is tested with a two-carrier wideband Wideband Code Division Multiple Access (WCDMA) signal.