Dynamic logic synthesis

A self-timed dynamic logic family, clock-delayed (CD) domino, was developed to provide non-dual-rail gates with inverting or non-inverting outputs. CD domino circuits are as easy to synthesize as static circuits and synthesis tools developed for static CMOS are used as part of a methodology for automating the design and synthesis of dynamic circuits. The methodology and CD domino's characteristics are demonstrated in the synthesis of five MCNC combinational logic benchmark circuits. Simulations of extracted chip layouts for the circuits show speed improvement factors of 2.17 to 6.28 compared to their static CMOS counterparts.