On-chip coupled noise analysis of a high performance S/390 microprocessor

A methodology based on closed form expressions and 3D capacitance extraction is used to predict noise and timing impact due to line to line coupling. In this paper, details of the methodology described include the quantification of closed form expressions used for noise voltage prediction, assumptions made to factor in uncertainties of the coupling topology and the databases used to improve the accuracy of this approach. A sophisticated 3D capacitance extraction process is also discussed in some detail. Other issues such as the timing impact due to noise are also examined by including additional equations which relate the delay adjustment due to the total noise for each net with minimal timing margin. Finally, a statistical summary of the number of nets being analyzed at the chip level, with associated pertinent parameters such as coupling coefficients and coupled segment information is also shown. Other details as macro coupled noise analysis are discussed in context to the limitation of the global methodology described with recommendations for future work in this area. Such an approach uniquely relates complex issues of on-chip noise prediction with sophisticated database manipulation and sound engineering judgement to provide a comprehensive solution to the problem at hand.