GSM-EDGE modulators for 2.5G system, an efficient parallel implementation on FPGA

This paper demonstrates an efficient parallel implementation of Gaussian Minimum shift keying (GMSK) and 8PSK modulators for Enhanced Data Rates for GSM Evolution (EDGE) systems. This method makes use of pre-calculated partial response Gaussian filter phase pulse shaping and Phase concatenation circuit accumulation for GMSK. EDGE-8PSK consists of combined gray coded 3π/8-rotated I-Q 8PSK mapping state machine circuitry and individual I&Q pulse shaping using optimized symmetrical FIR. The final output of both GMSK and 8PSK are multiplexed and selected as per requirement on slot basis control signal (Further these signals are given for up-conversion.) Hardware realization is done using VHDL; circuits are synthesized. Design is Prototyped in Altera Cyclone-3 FPGA (Field Programmable Gate Array), verified using R&S (Rhode and Schwarz) Vector signal analyzer. The design and hardware implementation of this modulator was done for indigenous GSM BTS (Base transceiver station) project.