Improved embedded EEPROM in 0.35μMCMOS technology with small-scale

This paper presents a low-power embedded EEPROM in a short-range passive RFID tag. This tag was designed according to ISO/IEC 15693 protocol. An improved structure of array circuit is proposed which can reduce leakage of memory bit cell efficiently. The proposed circuits can reduce maximum to 8 uA per bit cell. A new RFID EEPROM timing design and its optimized control circuit are developed. The fabrication technology is the 0.35-μm four-metal two-poly mixed signal CMOS process with embedded EEPROM. The low power consumption to erase /write is 38 μA, and reading power consumption is 2.2 μA at 2.6 V.