RSA encryption algorithm implemented on FPGA

In this paper is presented an efficient implementation of the Rivest, Shamir and Adleman (RSA) algorithm as a prototype programmable structure Xilinx Spartan3 to be integrated on an Application Specific Integrated Circuits (ASIC) structure. The purpose of this implementation was the optimization of the Field Programmable Gate Array (FPGA) area used. The paper describes the structures of the constituent modules of the RSA algorithm and obtained results are compared with other similar implementations, including bio-inspired ones based on cellular automata (CA).