A low power bulk-driven MDAC synapse

Efficient weight storage and multiplication are important design challenges which must be addressed in analog neural network implementations. Many schemes have been previously reported for implementation of synapses. In this paper we describe a buck driven Multiplier digital-to-analog converter (MDAC) circuit. We present a novel synapse circuit for analog neural networks. This circuit is a 6-bit Multiplier Digital to Analogue Converter (MDAC) synapse based on bulk-driven technology. The circuit has a small layout area (1200 μm2 using 0.18 μm TSMC CMOS technology). The measured results are within ±0.5 LSB for DNL and ±0.4 LSB for INL, with 0.1 mW power dissipation at 0.75 V power supply and the silicon area is reduced by a factor of 35% with respect to conventional MDAC implementation.