Predictive modeling of parasitic substrate currents in high-voltage smart power IC's

This paper presents a modeling methodology for substrate current coupling mechanisms. An equivalent schematic is made using enhanced model of resistances and diodes. These enhanced components were developed in previous work and account for minority and majority carrier propagation inside the semiconductor substrates. For the first time an equivalent schematic accounting for minority carrier is validated on an integrated circuit by modeling the current coupling occurring between two high-voltage H-bridges. The results obtained from the lumped model are in very good agreement with measurements. For the first time, a simulation methodology is proposed to accurately model substrate of smart power IC's using low computer resource.