Full link impedance optimization for serial IOs

In this paper, optimal impedance for interconnects, transmitter and receiver design is studied to improve link performance for high-speed differential signaling. Impedance lower than 100Ω for interconnect is shown to improve performance, even when other components such as transmitter, receiver, connector, cable, etc, are designed to 100Ω. Link performance can be further improved if transmitter and receiver can be tuned to impedance targets other than 100Ω. This study is supported by simulation and measurement of 6Gbps serial links, and by simulation of 12Gbps serial links.