Improvement of peak detection for digital storage oscilloscope

Peak detection is a powerful feature of digital storage oscilloscope. Traditional peak-detect mode has two shortcomings. First, the waveform is discontinuous in dot display mode. Second, the sampling and storing are running at different clocks. Metastability could emerge when sample data transfer across clock domains. FPGA-based digital storage enables designer to improve the waveform quality in peak detect mode. Aiming at the above problems, loading the previous peak data as reference point and using one clock wide pulse as clock enable are employed in a peak detect circuit. This circuit is disposed at the ADC outputs, and outputs maximum and minimum values. Moreover, this design is applied into a certain type of oscilloscope and verification results are provided.