Method to Design Arc Fault Detection Algorithm Using FPGA

The object of this paper is to present a method to design and to improve arc fault detection algorithm using FPGA devices. When designing an arc fault detection prototype, criteria such as detection reliability, detection speed and silicon occupation must be extracted to compare detection algorithm performances. We have developed a device which can execute and test the performances of algorithms with differents kind of power sources (AC and DC for domestic and aeronautic applications) and any loads. This prototype includes an analog part to carry out line voltage and current measurements (up to 270 V, up to 50 A, up to 1.5 MSPS). The digital part is built with an Altera Cyclone III FPGA circuit. An interface is added to control a contactor which protects the electric line. Algorithm implementation is carry out with VHDL We describe the algorithms in VHDL. The board architecture is characterized by low power consumption, high fonctionality and fast prototyping. Our prototype gives an effective and inexpensive means to design arc fault detection algorithms.