A medium-grain reconfigurable processor organization

In this paper a novel and extremely configurable execution core is presented for a standard five-stage pipelined processor. This processor implementation targets a medium grain highly reconfigurable hardware architecture that has been developed for DSPs applications. Using the Spec Espresso and Li benchmarks, analysis of different data forwarding mechanisms and machine per system clock factors are offered. Results show that with an increase in 16.7% or 28.7% hardware size execution time can be reduced by up to 10.79% and 15.63% respectively.