An LDPC decoder architecture for multi-rate QC-LDPC codes

This paper presents a partially parallel LDPC decoder architecture for QC-LDPC codes. In particular, we introduce a check node processing element which is 3-parallel, adjustable to irregular inputs and easily expandable. Furthermore, our decoder is applicable to multi-rate system by simply writing additional data to internal RAM. In another aspect of our work, we can reduce the check-bit message memory significantly by efficient method. Implementation results show that the proposed architecture can support the data rate of 360Mbps in FPGA.