A 1-V CMOS 65nm frequency synthesizer design with programmable acquisition speed

This paper presents a 24GHz PLL design featuring programmable acquisition speed using 65nm CMOS. In a high frequency PLL, the locking time is easily affected by the variation of oscillation frequency and K
_VCO
. To maintain the dynamic behavior of a PLL, two control parameters of its loop transfer function are used for programmability, including the charge pump current and pole-zero position. With an appropriate tuning mechanism, the loop bandwidth of the PLL can be modified from 0.94MHz to 2.05MHz, the phase margin can be maintained to be larger than 54degree, and the locking time can be varied from 1.75μs to 3.5μs for the 24GHz VCO. The PLL has a K
_VCO
tolerance from 1GHz/V to 2GHz/V. In both cases, the locking time can be 12% and 16% faster respectively. In three VCO operating scenarios with K
_VCO
of 1, 1.4, and 2GHz/V, the acquisition speeds of the PLL are in the range of 2.29μs to 2.36μs with merely 3% variation after adaption. The control mechanism can be applied to millimeter-wave frequencies with more strict locking time requirements and wider tuning range.