Design and implementation of charge-pump phase-locked loop

A phase-locked loop with charge pump approach is design and implemented using the TSMC 0.35 μm CMOS 2P4M process. The output frequency generated from the phase-frequency detector is compared with the reference frequency. This output frequency is then converted into current through the charge-pump. This current is further converted into voltage through loop filter to control oscillator. Because the output frequency is too high it is reduced by the frequency divider for comparison. According to simulated and measured results, the CPPLL centered at 500 MHz output frequency, chip size is 1.023×1.011mm², power dissipation about 10 mW, and the jitter is 80ps.