Data line driver design for A 10" 480/spl times/640/spl times/3 color FED

A data line driver with 120 outputs and capable of producing contrast ratio over 100 for a 10" 480/spl times/(640/spl times/3) pixels color field emission display (FED) panel have been designed. Phase clocks were used to reduce the maximum operating frequency to 22.68 MHz. A class AB op amp was used as the analog output buffer to reduce the power dissipation. The chip is implemented in a 24 V CMOS process, chip size is 7620 /spl mu/m/spl times/17500 /spl mu/m.