Fabrication of gated silicon spike emitter structures using micromachining mold technology

In order to reduce capacitance between emitter and gate electrodes, it is desirable to maximize the thickness of the oxide separating the electrodes. Parts with large (15 /spl mu/) emitter-to-gate electrode spacing have been fabricated using mold micromachining processes. The gates are self aligned to the emitter tip using CMP. The process results in planar features which are potentially compatible with CMOS processing.