Low voltage, low power analog multipliers based on CMOS inverters

In the paper we discuss low voltage, low power analog four quadrant multiplier based entirely on CMOS inverters. The circuit idea and simulation results has been already presented in another paper, here a new measurements results of the chip manufactured in 180nm CMOS technology from UMC are given. We also redesigned the circuit to suit it for another technology - 0.35μm CMOS from AustriaMicroSystems. The latter design has been a little bit more challenging because difference between absolute values of p-MOS and n-MOS threshold voltages is not negligible - on contrary to UMC. We also introduced some minor improvements to make the circuit manufacturable. Simulation results for the second technology are also presented.