A submicron Bi-CMOS-DMOS process for 20-30 and 50 V applications

This paper describes a high voltage process using 0.8 /spl mu/m technology for mixed signal applications. The technology allows the integration of high side 20, 30 and 50-V n-type LDMOS transistors and 50 V p-type LDMOS transistors along with dense logic/analog 5 V-CMOS and complementary low and high voltage bipolar transistors. Extended drain NMOS and PMOS transistors (ENMOS-EPMOS) whose safe operating areas exceed 50 V were also implemented. This technology is ideal for intelligent power application.