New dual gate-BRT structures with encased FBSOA

In order to improve the forward biased safe operating area (FBSOA) of the Dual Gate-BRT (DG-BRT) in IGBT mode, the characteristics of the three different kind of structures: (a) with low P-channel resistance (R/sub M/) under the off-gate; (b) low P-base resistance (R/sub B/) under the N/sup +/ emitter region; and (c) low P-base spreading resistance (R/sub S/) at the side of the N/sup +/ emitter region, were investigated by two-dimensional numerical simulation. It was found that reducing R/sub M/ by using the accumulation mode P-MOSFET results in a relatively small improvement in FBSOA but leads to a large snapback in the on-state J-V curve. On the other hand, reducing R/sub B/ and R/sub S/ using a highly doped P-base region or by including a subsurface P/sup +/ implant in the P-base region results in a large increase in FBSOA. An excellent current saturation is observed in the structure with higher P-base doping concentration and P/sup +/ subsurface implantation with no thyristor latch-up even for +15 V applied to the on-gate.