How many entries we need in miss handling architectures of L1 and L2 cache?

Recently-proposed processor micro-architectures for high Memory Level Parallelism (MLP) harvest substantial performance gains. Unfortunately, Miss-Handling architectures (MHAs) of current cache hierarchies are too limited to support the requirement of high MLP system. This paper proves the number relation of MHA entries between L1 and L2 cache, presents an algorithm to forecast the supremum of MHA entries. The analysis results present the MHA quantitative requirements for MLP processors. At last we valid the proved relation in experiment.