ASAver.1: an FPGA-based education board for computer architecture/system design

This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a pipelined RISC processor within limited time available for the course. The approach consists of 4 steps; at the first step, modeling of pipelined RISC processor is simplified by avoiding structural hazard and by ignoring other hazards, and in the succeeding steps, students learn difficulties of pipelining by themselves. An educational FPGA board ASAver.1 and results of feasibility study are also shown.