Dual-loop system of distributed microregulators with high DC accuracy, load response time below 500ps, and 85mV dropout voltage

A dual-loop architecture employs 8 distributed microregulators (UREGs) to achieve response times below 500ps in 45nm SOI CMOS. The trip point of an asynchronous comparator inside each UREG is tuned for high DC accuracy with a local charge pump, which receives UP/DOWN currents from a slow outer feedback loop. Measured DC load regulation is better than 10mV down to a dropout voltage of 85mV, and jitter readings in a CMOS delay line application indicate output noise below 28mVpp.