A 35 GHz dual-loop PLL with low phase noise and fast lock for millimeter wave applications

A fully integrated dual-loop PLL for mm-wave applications is presented. The design includes a phase locked hold loop and a frequency acquisition loop; by using two types of phase detectors for each individual loop, a low phase noise, a fast lock time, and a wide locking range can be achieved simultaneously. A method for phase noise optimization of the PLL is described. The chip was designed in a 250 nm SiGe BiCMOS technology. The locking range is from 33.8 to 37.6 GHz. The output phase noise is around -106 dBc/Hz at 1MHz offset.