16-Bit RISC processor design for convolution application

In this paper, we propose a 16-bit non-pipelined RISC processor, which is used for signal processing applications. The processor consists of the blocks, namely, program counter, clock control unit, ALU, IDU and registers. Advantageous architectural modifications have been made in the incrementer circuit used in program counter and carry select adder unit of the ALU in the RISC CPU core. Furthermore, a high speed and low power modified Wallace tree multiplier has been designed and introduced in the design of ALU. The RISC processor has been designed for executing 27-instruction set. It is expandable up to 32 instructions, based on the user requirements. The processor has been realized using Verilog HDL, simulated using Modelsim 6.2 and synthesized using Synopsys. Power estimation and area estimation is done using Synopsys Design Vision using SAED 90nm CMOS technology and timing estimation is done using Synopsys Primetime. In this paper, we have extended the utility of the processor towards convolution application, which is one of the most important signal processing application. The simulations depict the total dissipated power by the processor to be approximately 329.3 μW with the total area of 65012 nm².