Design of downlink PDSCH architecture for LTE using FPGA

The LTE specification provides a framework for increased capacity, improved spectrum efficiency, improved coverage, reduced cost per bit for the operator, and reduced latency compared with previous wireless implementations. The 3GPP LTE system should support instantaneous downlink and uplink peak data rates of 100Mb/s and 50Mb/s within 20 MHz downlink and uplink spectrum allocations, respectively. LTE allows operators to provide different services based on spectrum. LTE improves spectral efficiency in 3G networks. This paper focuses on the transmitter architecture of the downlink data channel PDSCH comprising Scrambling, Modulation, Layer Mapping, Precoding, addition of parity bits to precoded output and mapping to resource elements and receiver architecture comprising Demapping from Resource Elements, Removal of parity bits, Decoding, Delayer Mapping, Demodulation and Descrambling as described in the LTE specifications.