The 10 GHz wide tuning and low phase-noise PLL chip design

An integer-N phase-locked loop (PLL) operating at 10 GHz is designed and fabricated in TSMC 0.18-um CMOS technology. The proposed PLL with a LC-tank voltage-controlled oscillator (VCO) and a mixed design of current mode logic (CML) and true single phase clock (TSPC) logic in the frequency divider achieves a tuning range from 8.75 GHz to 10.93 GHz and a phase noise of −113.4 dBc per Hertz at an offset frequency of 1 MHz from the carry frequency of 10.49 GHz. The final simulated locking time is lower than 3.7 us. Including pads and an on-chip third-order low-pass filter, the overall chip area is only 0.82×0.68 mm
²
(0.56 mm
²
) as well as the power consumption is 39 mW at the 1.8 V supply voltage.