Parallel positive justification in SDH C-4 mapping

Bit rate justification is a key technique in digital multiplexing. SDH adopts positive justification for C-4 mapping and positive/zero/negative justification for other mappings. The mapping of C-4 has the highest system frequency in all bit rate justifications of SDH. This demands highly on the technology and power consumption in the ASIC design. This paper puts forward a novel technique of positive justification with parallel processing and solves the problem caused by high speed. This method is very useful for implementing the C-4 mapping with CMOS gate array technology. The design has been implemented with FPGAs of Xilinx Inc. The paper ends with the mapping jitter test results, which are quite satisfied.