Scalable Transactional Memory Architecture Supporting Speculative Parallelization

Traditional parallel programming complexity and its constraints on performance facilitate the thread level speculation (TLS) and transactional memory (TM) technology. It's reasonable to combine the benefits of them for exploiting more thread-level parallelism from multi-core architecture. This paper proposes a novel scalable transactional memory architecture supporting speculative parallelization, including its special hardware, compiler and execution support. It's a unified model that supports both TLS and TM semantics with minimal hardware overhead that would help simplify hardware design and improve the system interoperability. PTT makes two additional contributions. First, it proposes a directory-based cache coherence protocol supporting priority determination to achieve the hardware distributed arbitrating mechanism. Second, PTT reduces the complication and complexity of parallel programming work, thus greatly improving parallel programming productivity. The evaluation shows that the new system performs well in most suitable benchmarks, resulting liner growth speedups with increasing cores.