A new approach in the implementation of test generation algorithms for programmable logic arrays

A new approach was used in the development of the implementation of a minimal test vector generation algorithm for single and multiple fault detection in a PLA. The conversion of product terms from binary notation to decimal notation simplifies the development of the C language subroutines used for the implementation. The ordered position in our approach allows us to find a complete test vector in a single comparison in some instances and makes it feasible to find complete test vectors having a d/sub H/=k in an n-dimensional subspace, e.g. even if 99.21875% of the minterms in an 8-dimensional subspace are bounded.