An 8-bit 42 Msamples/s current-mode folding and interpolation CMOS analog-to-digital converter with three-level folding amplifiers

A low power 8-bit current-mode folding and interpolation analog to digital converter (ADC) with three-level folding amplifiers is presented in this paper. A three-level folding amplifier is designed not only to reduce the number of reference current sources, but also to decrease power dissipation within the ADC. A newly designed delay time error correction circuit is employed to make delay time error correction between the coarse quantizer and the fine quantizer. The simulation results illustrate a conversion rate of 42 MSamples/s and a power dissipation of 30 mW.