A multiplier and squarer generator for high performance DSP applications

A generator for multiplier and squarer structures, suitable for high performance bit-parallel DSP applications in VLSI, is presented. The squarer structure employs a novel bit-parallel partial product reduction scheme, reducing delay and hardware by 50%, compared to a full multiplication. The generator is based on optimized Wallace trees, Booth encoding and binary tree vector merging addition. Computation of weighted square sums is used as a design example, which has applications in e.g. pattern recognition. Results indicate a delay reduction of 10-20% compared to traditional designs for high speed, as well as a reduction in power and area, for a standard 0.8 /spl mu/ CMOS process.