A pulse processing station

This is the first of two papers concerning the architecture, circuitry design and performance of a pulse processing system based on a digital signal processor. This multifunction system, implemented as a single PC module, incorporates a high performance 16-bit Pulse Height Analyser (PHA) a Multichannel Scaler (MCS), a Digital Oscilloscope (DSO) and also a Digital Pulse Processor (DPP). This paper presents the PHA architecture with emphasis on the baseline restorer and peak stretcher circuits. Differential nonlinearities (DNL) are corrected by a new implementation of the sliding scale technique and performance ranges from better than 2% (at 16-bit resolution) up to less than 0.2% for 12-bit operation. The DNL correction technique is assessed for different sliding-scale ranges.