A single-chip stereo audio codec

Attention is given to a 16 b stereo audio codec that integrates two delta-sigma ADCs (analog-to-digital converters), two delta-sigma DACs (digital-to-analog converters), DAC analog postfilters, a voltage reference, and 64X digital interpolation and decimation filters. The delta-sigma modulators use single-loop fourth-order topology at a 64X oversampling rate. The DAC analog postfilters reduce sharp-rising quantization noise and improve timing jitter sensitivity. ADC and DAC dynamic ranges (0-22 kHz) are 88 dB and 87 dB, respectively. The 24.8 mm/sup 2/ chip is implemented in a 1.6 /spl mu/m double-poly, double-metal CMOS process.