An enhanced successive-approximation circuit for A/D conversion

A modified successive approximation A/D (analog-to-digital) converter is introduced which employs parallel analog comparators to reduce the number of compare cycle from N to N/s for an N-bit digital code. Unlike the case of traditional flash/successive-approximation techniques, the additional comparators have a very low accuracy requirements and in general can be designed using digital, rather than analog, design rules and techniques. Using a predictive approximation approach it is not unreasonable to expect a 40% decrease in total cycle time, including logic delays, compared to a conventional successive-approximation converter.