High performance BiCMOS technology

The authors describe the process integration issues of high-performance BiCMOS technologies intended to be used not only in high-density digital applications but also in high speed ECL (emitter coupled logic) and mixed analog/digital signal applications. In particular, they describe a half-micron super-self-aligned BiCMOS technology with bipolar f/sub max/ of 34 GHz and a CMOS gate delay of 50 psec. Circuit applications for multi-gigahertz communication are presented to show the potential of high-performance BiCMOS technology.